1. Field of the Invention
The invention relates generally to semi-conductor memory devices. Particularly, the invention relates to Electronically Erasable Programmable Read-Only Memory (E.sup.2 PROM) or Electrically Alterable Read-Only Memory (EAROM) and to non-volatile random access memory (NVRAM).
2. Prior Art
U.S. Pat. No. 4,458,407 (entitled "Process for Fabricating Semi-Conductive Oxide Between Two Polysilicon Gate Electrodes," filed on Apr. 1, 1983, issued July 10, 1984 to Hoeg et al, and assigned to the assignee of the present invention) sets forth a full description of the prior art and should be referred to for prior art information. The subject patent is incorporated herein by reference.
As is noted in the Hoeg, Jr. et al patent, in fabricating a semiconductive oxide or Dual Electron Injection Structure (DEIS) between two polysilicon electrodes, it is necessary to protect the DEIS from oxidation during the step of growing the gate oxide for the second polysilicon electrode. The DEIS material, as taught by DiMaria (a reference described in the prior art section of the Hoeg et al reference), is a composite of three layers of silicon dioxide which have been chemically vapor deposited such that the bottom and top layers have excess silicon atoms which when placed adjacent to lower and upper conductive electrodes of polysilicon cause a conduction of electrons through the middle silicon dioxide layer at a reduced electric field. The middle layer inhibits the tunneling of charge at lower electric fields and as a result prevents the loss of charge from a floating gate in a non-volatile memory cell. This composite structure readily oxidizes to silicon dioxide during a typical gate oxidation step unless protected by a non-oxidizing layer.
A method for fabricating the DEIS between Poly 1 and Poly 2 devices has been taught in the Hoeg Jr. et al patent. The method uses a layer of silicon nitride to prevent oxidation of the DEIS during the required oxidation step. The Hoeg et al reference also teaches the removal of the silicon nitride layer using a combination of plasma etch and hot phosphoric acid which attacks the exposed gate and insulator layer. The patent also teaches the use of a thin poly X layer as a buffer between the silicon nitride and the DEIS to protect the DEIS from the etching steps.